One problem that is confronting the semiconductor processing industry in the age of ultra large scale integration (ULSI) is capacitive-resistance loss in wiring levels. Conventionally, aluminum and aluminum alloys have been used for semiconductor wiring. In an effort to improve conductivity, it has been suggested to substitute copper metallurgy for aluminum metallurgy.
However, problems have been encountered in developing copper metallurgy. One problem is that copper quickly diffuses through both silicon and silicon dioxide (SiO2). Another problem is the known junction poising effects of copper. It has been proposed to use a liner to separate the copper metallurgy from the SiO2 insulator. Proposed liners include either a metal such as tantalum (Ta) or tungsten (W), or a compound such as tantalum nitride (TaN) or silicon nitride (Si3N4). Another problem is that copper, unlike aluminum, does not form a volatile compound at room temperature and thus cannot be reactively ion etched. The “damascene” process has been used to form copper lines embedded in an insulator. In this process, a layer of insulator is deposited, and trenches for conductors are formed in the insulator using a resistive ion etching (RIE) process. A liner and adhesion layer is deposited, and copper is blanked deposited by either chemical vapor deposition (CVD) or electroplating. The unwanted copper and liner is then removed by a chemical mechanical polishing (CMP) process.
CMP is a semiconductor wafer flattening and polishing process that combines the chemical removal of semiconductor layers such as insulators and metals with the mechanical buffering of a wafer surface. Typically, CMP is used to polish or flatten wafers after crystal growth during the wafer fabrication process, and to polish or flatten the profiles that build up in multilevel metal interconnection schemes.
A traditional CMP tool has a hard surface platen onto which the wafer is fixed. A polishing abrasive is applied and a polishing pad, which may contain additional abrasive, is moved over the wafer surface. The polishing solution containing the abrasive is, at least to some extent, generally reactive to the materials being polished. In one known polishing system, the abrasive is fixed to the pad and the pad is immersed in a liquid. This pad is then used in a similar method as the other systems.
In many CMP systems, the wafer platen and the polishing pad are rotated during the polishing process. Some designs have used a belt that contains an abrasive material. These systems have been used to achieve a significant degree of local planarization as well as limited long range planarization. However the degree of long range planarization has been significantly less than desired. Additionally, other non uniformity problems such as dishing and rounding of the features tend to occur. These non uniformity problems result in uneven surfaces and layers that are not uniformly thick. This is a significant problem for achieving complete planarization.
Therefore, there is a need in the art to provide a CMP system and process that overcomes the problems of uneven surfaces and increases the degree of long range planarization.